A multi-gate transistor has been proposed as a potential technique for increasing the density of integrated circuit devices. A multi-gate transistor has a fin-shaped or nanowire-shaped semiconductor body that is formed on a substrate and a gate is then formed on a surface of the semiconductor body. Since multi-gate transistors use three-dimensional (3D) channels, scaling of the multi-gate transistor is easily achieved. In addition, current controlling capability can be improved without increasing a gate length of the multi-gate transistor. Further, a short channel effect (SCE), in which an electric potential of a channel region is affected by a drain voltage, can be suppressed in multi-gate transistors.